The present invention relates to a semiconductor integrated circuit in which a plurality of circuit blocks (digital circuits) to which reference clock signals with different frequencies are input are fabricated on the same semiconductor substrate. More particularly, this invention relates to a semiconductor integrated circuit for use when a timing generator and a synchronizing (sync) signal generator used to generate a CCD (charge coupled device) image sensor drive pulse are fabricated on the same semiconductor chip.
Digital circuits to which reference clock signals with different frequencies are input, e.g., a timing generator and a sync signal generator used to generate a CCD image sensor drive pulse, are fabricated on respective semiconductor substrates and are mounted on a CCD image sensor set (video camera circuit board) as two semiconductor chips.
In order to miniaturize the CCD image sensor, efforts are made to form the timing generator and the sync signal generator as one semiconductor chip.
An arrangement in which a timing generator and a sync signal generator are fabricated as one semiconductor chip will be described with reference to a cross-sectional view of FIG. 1 and a circuit diagram in FIG. 2. In FIGS. 1 and 2, in order to facilitate the understanding, arrangements of a timing signal generator 101 and a sync signal generator 102 are illustrated as CMOS (complementary metal oxide semiconductor) inverters 103 and 104 which are elements of the respective generators 101 and 102.
As shown in FIG. 1, first and second N-type well regions 112An, 112Bn are formed on a P-type silicon substrate 111, for example, at its portion in which the timing generator 101 and the sync signal generator 102 are formed. First and second P-channel MOSFETs (referred to hereinafter as "first and second PMOSFETs") 113, 115 are formed on the N-type well regions 112An, 112Bn. First and second N-channel MOSFETs (referred to hereinafter as "first and second NMOSFETs") 114, 116 are formed on the P-type silicon substrate 111, thereby forming the timing generator 101 which includes the first CMOS inverter 103 composed of the first PMOSFET 113 and the first NMOSFET 114 and the sync signal generator 102 which includes the second CMOS inverter 104 composed of the second PMOSFET 115 and the second NMOSFET 116.
As shown in FIG. 2, an input voltage Vin1 is applied to gate electrodes 113G, 114G of the first PMOSFET 113 and the first NMOSFET 114 in the first CMOS inverter 103. A supply voltage VDD1 (=+5 V) is applied to a source electrode 117s which contacts a source region 113S of the first PMOSFET 113. A drain electrode 117d which contacts a drain region 113D of the first PMOSFET 113 and a drain electrode 118d which contacts a drain region 114D of the first NMOSFET 114 are connected commonly and an output voltage Vout1 is obtained from this common terminal.
An input voltage Vin2 is applied to gate electrodes 115G, 116G of the second PMOSFET 115 and the second NMOSFET 116 in the second CMOS inverter 104. A supply voltage VDD2 is applied to a source electrode 119s which contacts the source region 115S of the second PMOSFET 115. A drain electrode 119d which contacts the drain region 115D of the second PMOSFET 115 and a drain electrode 120d which contacts the drain region 116D of the second NMOSFET 116 are commonly connected and an output voltage Vout2 is obtained from this common terminal.
A ground potential VSS (=0 V) is applied to source electrodes 118s and 120s which contact the source regions 114S and 116S of the respective NMOSFETs 114, 116. Simultaneously, the ground potential VSS is applied to the silicon substrate 111 as a substrate potential. Specifically, the same supply potential (ground potential VSS) is applied to the source regions 114S, 116S of the respective NMOSFETs 114, 116.
In the semiconductor integrated circuit, when the potential Vin1 input to the first CMOS inverter 103, for example, goes to a high level so that the first NMOSFET 114 is operated, the substrate potential VSS is fluctuated in accordance with charges (electrons in this case) induced under the gate electrode 114G of the first NMOSFET 114 from the silicon substrate 111. A timing at which the substrate potential Vss is fluctuated is determined by the change of level of the input voltage Vin1, i.e. the frequency of the reference clock signal supplied to the timing generator 101.
The fluctuation of the substrate potential VSS is transmitted through the silicon substrate 111 to the second CMOS inverter 104, so that a gate bias potential and a source voltage in the second NMOSFET 116 is fluctuated. Consequently, as shown in FIG. 3B, a waveform distortion a (so-called beat) b is caused in the output potential output from the second CMOS inverter 104 due to potential interference.
This phenomenon occurs also in the first CMOS inverter 103. As a result, as shown in FIG. 3A, the beat b occurs also in the output potential output from the first CMOS inverter 103. This phenomenon of the beat b occurs because operation timings of the first CMOS inverter 103 and the second CMOS inverter 104 are different, i.e., a frequency (=28 MHz) of a reference clock signal supplied to the timing generator 101 including the first CMOS inverter 103 and a frequency(=17 MHz) of a reference clock signal supplied to the sync signal generator 102 including the second CMOS inverter 104 are different from each other.
The beat b exerts a bad influence on the CCD image sensor and is superimposed on video signal as a noise. As a result, when the cameraman takes a picture of a white object by a video camera, as shown in FIG. 4 many oblique dark stripe patterns c are produced in a picture reproduced on a monitor so that a picture quality of a reproduced picture is deteriorated considerably.
Therefore, a plurality of circuit blocks (the timing generator 101 and the sync signal generator 102 in this example) to which the input reference clock signals with different frequencies are input could not be fabricated on the same substrate 111. Thus, the CCD image sensor could not be miniaturized from a circuit mounting standpoint.